The Switzerland of Physical AI: Why QNX Wins the Chip War by Not Fighting It

NVIDIA, AMD, Qualcomm and MediaTek are fighting over the AI chip. QNX is quietly running on all of them.

By The 🍌🐀 (The Banana Rat)

Scope & disclosure. A forward-looking editorial thesis on market structure in edge-AI compute — not investment advice. As-of date: 2026-07-01. Factual claims are sourced in the endnotes; inferences are labeled as thesis. Conflict-of-interest disclosure: the author holds a position in BlackBerry (BB), whose QNX division is discussed below. Do your own research.

Part of the 🍌🐀 Physical AI & Edge Compute field guide → the hub for the whole thesis.

Every headline about physical AI is a headline about silicon. NVIDIA briefly touched $5.5 trillion. AMD is loudly carrying x86 into robots and cars. Qualcomm and MediaTek are stuffing the mass-market dashboard. The whole industry is craning its neck at one question: which chip wins?

The 🍌🐀 wants you looking one layer up, at the question nobody’s asking: whatever chip wins, what does it have to run to be allowed to move a two-ton machine? Because the answer to that one is turning into a business that doesn’t care who wins the first one.

The tollbooth that isn’t made of silicon

Here’s the thesis, and I’ll flag up front that the “Switzerland” framing is my read of a dated support pattern, not a slogan QNX prints on its slides. In a physical-AI system, the intelligence and the safety are two different jobs on two different clocks. The brain (perception, planning, the generative model) is probabilistic and lives on the fastest, hungriest silicon you can afford. The reflex (the certified, deterministic layer that guarantees the machine stops, holds, or hands off safely when the brain is wrong) is a separate function with a separate, brutal requirement: it has to behave identically every time, and it has to carry the certification evidence a regulator will demand.

The silicon war is a war over the brain. The reflex is a different tollbooth on the same road — and it is largely indifferent to which brain won. That’s the layer QNX has spent two years making itself run on everywhere.

Start with NVIDIA, the brain everyone is buying

The most important seat QNX holds is under the most important brain. NVIDIA has become the default compute platform for physical AI, and QNX rides in its safety seat. QNX OS for Safety 8.0 is integrated with NVIDIA’s Thor platform in both worlds: the car (DRIVE Thor) and the robotics, medical and industrial edge (IGX Thor), and in 2026 it moved into NVIDIA’s Halos safety stack [3]. The split is the whole thesis in miniature: NVIDIA’s silicon runs the probabilistic AI brain, and a certified real-time OS runs the deterministic safety reflex right beside it, walled off so a fault in one cannot take down the other.

Here is what makes it a business rather than a favor: NVIDIA does not own that safety layer, and by the architecture of its own reference designs it does not try to. DriveOS hands the certified real-time slot to a safety OS, Linux or QNX [6]. The compute kingmaker builds the brain and rents the reflex from someone else, and QNX is the incumbent tenant for that seat. Owning the safety seat under NVIDIA is the single most valuable position in physical AI that NVIDIA itself has chosen not to fill.

Then AMD, which proves QNX isn’t captive to one vendor

A safety layer that only ran on NVIDIA would just be an NVIDIA accessory. The real tell that QNX is genuinely silicon-neutral is that the same certified layer also runs on NVIDIA’s fiercest architectural rival. You don’t prove neutrality on one vendor’s chip; you prove it on the chip built by that vendor’s biggest competitor. That is why the AMD story matters more than it looks.

QNX has walked its safety-certified Software Development Platform (SDP 8.0) straight across AMD’s compute portfolio, one architecture at a time:

• April 2024 — robotics. At Embedded World in Nuremberg, QNX and AMD paired SDP with the AMD Kria adaptive module (Arm cores plus FPGA logic) for low-latency, low-jitter robotic control — sensor fusion, real-time control, industrial networking [1].
• March 2025 — adaptive compute. QNX extended SDP 8.0 to AMD’s Versal and Zynq UltraScale+ adaptive SoCs, with AMD running the deep-learning navigation and object-detection workloads while QNX owned deterministic scheduling and motion control [1].
• March 2026 — x86. QNX added support for AMD Ryzen Embedded V2000 and announced intent to support the Ryzen AI Embedded P100 — pitching it as an “x86 alternative for consolidated, real-time embedded systems” across automotive digital cockpits, industrial and robotics controllers, and medical imaging [1].

The tell is in who said what. AMD’s spokesman on the 2026 release is Simon George, whose title is now Director of Embedded Systems, Physical AI — and he framed future QNX support for the P100 as letting it “allow precise resource allocation and deterministic performance for mission and safety critical AI workloads” [1]. That’s the silicon vendor itself describing QNX as the safety-and-determinism discipline on top of its AI compute. The P100, for its part, is no toy: AMD rates the family at up to 80 total system TOPS across CPU, GPU and an XDNA 2 neural engine, and markets it explicitly as “physical AI” silicon [2].

So on AMD alone, QNX now spans FPGA, adaptive SoC, and x86 — three different ways of building an AI machine, one certified safety layer across all of them.

And it doesn’t stop at those two

Widen the lens further and the pattern is unmistakable. Across the leading AI-compute vendors, the same QNX safety runtime keeps showing up:

No single row is a disclosed royalty win. But together they are the whole argument: the certified safety layer is becoming the one constant while the silicon underneath it turns into a field of interchangeable options.

Why neutrality is the moat

There’s a companion piece to this one where the 🍌🐀 argues NVIDIA is becoming the Wintel of physical AI — the compute standard that wins no matter which carmaker wins: NVIDIA Owns the Standard, Not the Car. This is the sequel. NVIDIA owns both of Wintel’s decks at once, the silicon and the platform software — a tighter grip on the standard than Intel and Microsoft ever had apart. But physical AI adds a toll the PC era didn’t have: the certified safety layer, which by the architecture of NVIDIA’s own reference designs is handed to a safety OS, Linux or QNX — not kept in-house.

That’s the beauty of the neutral position: an arms dealer of safety doesn’t have to pick the winning army. AMD’s pitch is x86 compatibility, workload consolidation, and long-lifecycle industrial support — it is explicitly carrying x86 into robots and cars against NVIDIA’s Arm-based Jetson and DRIVE; NVIDIA’s counter is raw throughput measured in thousands of AI TFLOPs [5]. A machine builder betting on either (or hedging across both, or dropping to Qualcomm for the mass-market tier) still needs the same certified reflex underneath. QNX doesn’t need to be right about the chip. It needs the chip to need it.

The honest hedge

This is a strategic position, not a booked quarter, and the calibrated version says so plainly:

• Support is not the same as paid design wins. Every AMD milestone is non-exclusive platform enablement (board support and a P100 roadmap) with no disclosed customer, design win, or revenue [1]. Breadth of support is the leading indicator; disclosed cross-silicon design wins are the confirmation, and they aren’t here yet.
• The P100 is a roadmap, not a shipment. QNX supports Ryzen Embedded x86 (V2000) today; P100 support is announced intent [1][2].
• QNX isn’t the only one who can play Switzerland. Certified Linux (Red Hat at ASIL-B), Wind River, SYSGO and Green Hills all chase the same silicon-neutral safety slot (and NVIDIA’s own DRIVE OS explicitly enables Linux or QNX [6]), so QNX’s edge is the ASIL-D microkernel pedigree and the installed base, not a monopoly on the idea.
• The framing is mine. QNX markets “parity between cloud and in-vehicle silicon”; it does not call itself “silicon-agnostic.” That word is the 🍌🐀’s inference from a real, dated support pattern — treat it as analysis, not a company claim.

Actionable Takeaway: the bull signal here isn’t “QNX supports AMD.” It’s whether breadth of silicon support converts into disclosed, paid cross-silicon design wins. Watch for a named customer shipping QNX on AMD (or Qualcomm, or MediaTek) the way BMW ships it on its Neue Klasse architecture. Support across the field is the setup; a paid win off NVIDIA is the tell that neutrality is a business, not just a brochure.

The full BlackBerry/QNX thesis (the growth models, the certification moat, and the honest “10× bigger” test) lives in the pillar: QNX: The Quiet Operating System Powering the AI Age.

The 🍌🐀 has spoken. 🍌🐀

Sources

[1] QNX + AMD collaboration (non-exclusive platform enablement; no disclosed customers/design wins/revenue at any milestone): (a) Apr 9 2024, Embedded World Nuremberg — robotics on the AMD Kria K26 SOM / KR260 starter kit (Arm + FPGA); quotes Chetan Khona (AMD), Grant Courville (QNX). PR Newswire, Apr 9 2024. https://www.prnewswire.com/news-releases/blackberry-announces-collaboration-with-amd-to-advance-foundational-precision-and-control-for-robotics-industry-302110129.html (b) Mar 11 2025 — QNX SDP 8.0 extended to AMD Kria SOMs, Zynq UltraScale+ and Versal adaptive SoCs; quotes Simon George (AMD), John Wall (QNX). AccessWire, Mar 11 2025. (c) Mar 10 2026 — SDP 8.0 for AMD Ryzen Embedded V2000 (x86), with Ryzen AI Embedded P100 support planned; verticals = automotive digital cockpits, industrial/robotics controllers, medical imaging; Simon George (Director of Embedded Systems, Physical AI, AMD): QNX P100 support “allows precise resource allocation and deterministic performance for mission and safety critical AI workloads and applications.” StockTitan (BB) / AccessWire, Mar 10 2026. https://www.stocktitan.net/news/BB/qnx-and-amd-empower-developers-with-high-performance-deterministic-qvwup9s3fq0v.html

[2] AMD Ryzen AI Embedded P100 Series: up to 80 total system TOPS across CPU (up to 12 “Zen 5” cores), GPU (RDNA 3.5) and NPU (XDNA 2, up to ~50 TOPS on the NPU alone); marketed for edge/”physical AI” (robotics, machine vision/SLAM, industrial, medical imaging, automotive). Introduced at CES 2026 (Jan 5 2026), expanded Mar 9 2026; mass production scheduled ~July 2026. AMD product page + blog + CNX-Software, Mar 2026. https://www.amd.com/en/products/embedded/ryzen-ai/p100-series.html

[3] QNX OS for Safety 8.0 integrated with NVIDIA IGX Thor and the NVIDIA Halos Safety Stack for regulated edge-AI systems; non-exclusive, Early Access, no disclosed design wins or revenue. QNX/NVIDIA press release, Apr 20 2026. https://qnx.software/en/press-release/2026/qnx-and-nvidia-deepen-collaboration-to-advance-safety-critical-edge-ai-across-robotics-medical-and-industrial-systems

[4] QNX Cabin runtime demoed across leading automotive SoCs (Qualcomm, AMD, MediaTek), and QNX Cabin for Cloud via AWS and Ampere, at CES 2026. QNX CES 2026 highlights, Jan 2026. https://qnx.software/en/blog/2026/qnx-at-ces-2026-highlights

[5] AMD positioning “x86 into robotics and cars, challenging Arm-based rivals” (i.e., NVIDIA’s Arm-based Jetson/DRIVE); NVIDIA leads peak edge-AI throughput while AMD differentiates on x86 compatibility, workload consolidation and industrial longevity. TechTimes, Jun 10 2026. https://www.techtimes.com/articles/318134/20260610/amd-carries-x86-robotics-cars-ryzen-ai-embedded-challenging-arm-based-rivals.htm

[6] Competitive context for silicon-neutral safety software: NVIDIA DRIVE OS enables Linux or QNX as the application OS; certified-Linux (Red Hat, ISO 26262 ASIL-B), Wind River, SYSGO and Green Hills also compete for the certified real-time slot. NVIDIA DRIVE OS SDK; ABI Research RTOS assessment, 2026. https://developer.nvidia.com/drive/os